CY28551LFXC-3T【PDF 9/28 页】IC CLOCK INTEL/AMD SIS VIA 56QFN

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CY28551-3

....................Document #: 001-05677 Rev. *D Page 17 of 28

CPU_STP# Assertion

The CPU_STP# signal is an active low input used for

synchronous stopping and starting the CPU output clocks

while the rest of the clock generator continues to function.

When the CPU_STP# pin is asserted, all CPU outputs that are

set with the SMBus configuration to be stoppable via assertion

of CPU_STP# will be stopped after being sampled by 2-6

rising edges of the internal CPUC clock. The final state of the

stopped CPU clock is Low due to tristate, both CPUT and

CPUC outputs will not be driven.

CPU_STP# De-Assertion

The de-assertion of the CPU_STP# signal will cause all CPU

outputs that were stopped to resume normal operation in a

synchronous manner. Synchronous manner meaning that no

short or stretched clock pulses will be produce when the clock

resumes. The maximum latency from the de-assertion to

active outputs is between 2-6 CPU clock periods (2 clocks are

shown). If the control register tristate bit corresponding to the

output of interest is programmed to '1', then the stopped CPU

outputs will be driven high within 10ns of CPU_Stop#

de-assertion to a voltage greater than 200mV.

PCI_STP# Clarification

The PCI_STP# signal is an active low input used for cleanly

stopping and starting the PCI and PCIEX outputs while the rest

of the clock generator continues to function. The PCIF and

PCIEX clocks are special in that they can be programmed to

ignore PCI_STP# by setting the register bit corresponding to

the output of interest to free running. Outputs set to free

running will ignore both the PCI_STP# pin.

PCI_STP# Assertion

The impact of asserting the PCI_STP# signal will be the

following. The clock chip is to sample the PCI_STP# signal on

a rising edge of PCIF clock. After detecting the PCI_STP#

assertion low, all PCI and stoppable PCIF clocks will latch low

on their next high to low transition. After the PCI clocks are

latched low, the stoppable PCIEX clocks will latch to low due

to tristate as show below. The one PCI clock latency as shown

is critical to system functionality, any violation of this may result

in system failure. The Tsu_pci_stp# is the setup time required

CPU_STP#

CPUT

CPUC

Figure 5. CPU_STP# Assertion Timing waveform

C P U _ ST P#

CP UT

CP U C

CP UT In t e r n a l

T d r iv e _ C P U _S T P #, 10n S > 200 m V

CP U C In t e r n a l

Figure 6. CPU_STP# De-Assertion

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